Achronix and ViASIC worked closely together to modify and integrate ViaPath’s place and route code base for use in ACE.  ACE is the Achronix design environment for its recently announced Speedster 1.5 GHz FPGA family.

According to Raymond Nijssen, chief software architect at Achronix Semiconductor, “To enable the world’s fastest FPGAs we looked for an EDA partner we could rely on to deliver place and route capabilities as early as possible in our software development cycle.  Our close collaboration in adapting the underlying engines and algorithms of ViaPath for Speedster has resulted in a powerful development tool. ViASIC exceeded our expectations.”

Mark Goode, president and CEO of ViASIC, said, “We were honored to work hand-in-hand with Achronix as part of its development team and contribute our knowledge of configurable silicon products. And we were pleased to provide the P&R backbone that became an integral part of the Achronix software tool suite. We congratulate Achronix on its innovation in bringing the Speedster family to market, and feel proud to be a part of that effort.”

Lynn Hayden, chairman of the board, and formerly president and chief executive officer at ViASIC said, “With his broad skills and keen business acumen, Mark Goode is the ideal person to guide ViASIC through its business development and next phase of growth. ViASIC continues to add value for its customers in the radiation hardened market with its configurable technology and will apply this capability more broadly for commercial applications.”

Goode has held board positions in seven companies and non-profit organizations. Prior to ViASIC, he was director of the Oak Ridge Design Center for Flextronics, and director of the FORGE Team, a high-end, customer-solutions-oriented ASIC task force. He co-founded ASIC International, Inc. (Ai) in 1993, and served as vice president of engineering before the company was sold to Flextronics in May 2001. An entrepreneur, Goode also has founded and assisted multiple successful companies and organizations. He holds a bachelor’s degree in music from University of Miami, a masters degree in computer science from New Jersey Institute of Technology, and a masters degree in business administration from the Wharton School at the University of Pennsylvania.

Speaking about his new roles, Goode said, “ViASIC is in a unique position to help leading-edge companies reduce non-recurring engineering and development costs by up to 95 percent, and significantly improve their time to market. I am honored to be part of the team that made this possible. ViASIC is committed to serving its customers worldwide, and I look forward to leading this effort.”

“I am honored to serve as president and CEO, and deeply committed to help leading-edge customers achieve their time-to-market goals,” said Hayden. “ViASIC’s unparalleled combination of low mask charges, ease of use, high density, risk mitigation and reconfigurability offers the best overall balance for general production. Also, our ability to reconfigure a design in less than a month uniquely positions ViASIC to help companies reduce mask costs and increase productivity so they can get to market sooner.”

Prior to ViASIC, Hayden served for 20 years as president and CEO of Coiltronics, a company he founded in 1977 shortly after his student days at Central Michigan University and sold to a large multinational corporation in 1997. Under his direction, it grew from a small regional supplier of relay coils to an international manufacturer and supplier of high-frequency electromagnetic components, becoming the largest supplier of its kind in the U.S.

For seven metal processes DuoMask uses via layers 2 and 4 to program the pre-built and pre-characterized logic and routing. The configurable logic is built upon existing technologies providing an accurate, proven fabric almost immediately for any process. The new configurable logic libraries require no logic cell layout, timing or power characterization; instead they rely on dependable, proven existing libraries. DuoMask is the densest standard-metal fabric available with 150K gates per mm2 at 90nm.

“DuoMask provides affordable two mask customization for every digital process”, said Bill Cox, CTO, ViASIC. “We are excited to provide this new technology which supports virtually anyone, in any process, at any fab and best of all it relies on existing proven and characterized libraries”

Configurable fabrics are one method that SoC designers can leverage their IP with low-cost, low-risk respins that empower customization of existing designs and rapid, easy addition of new features, expanding available markets for this IP. Configurable SoC’s use standard-cell flows to build the majority of the chip. Implementing the proven, stable blocks with classic methodologies, only a portion of the chip is built with a configurable fabric. This configurable portion of the SoC can then be used to implement a variety of functions that could be subject to change. With SoC configurability, designers can now get initial versions of a product out before final specs are set, getting hot products to market first.

DuoMask, along with ViASIC’s one-mask library ViaMask, and ViaPath, a place and route tool for standard-metal will be demonstrated at the Design Automation Conference in San Francisco on July 24 at booth 1108. To set up a private suite appointment email dac@viasic.com. For more information on the conference visit www.dac.com.

Price and Availability
DuoMask is immediately available for all digital processes between .35 micron and .45 nanometers. U.S. pricing starts at $95,000.